Click Here for
Track Your Paper

International Journal of New Technology and Research

Impact Factor 3.953

(An ISO 9001:2008 Certified Online Journal)
India | Germany | France | Japan

Verification of Identity and Syntax Check of Verilog and LEF Files

( Volume 4 Issue 2,February 2018 ) OPEN ACCESS

D. A. Simonyan


The Verilog and LEF files are units of the digital design flow [1][2]. They are being developed in different stages. Before the development of the LEF file, the Verilog file passes through numerous steps during which partial losses of information are possible. The identity check allows to make sure that during the flow the information has not been lost. The syntax accuracy of the Verilog and LEF files is checked as well.

            The scripting language Perl is selected for the program. The language is flexible to work with text files [3].

            The method developed in the present paper is substantial as the application of integrated circuits today is actual in different scientific, technical and many other spheres which gradually finds wider application bringing about large demand.

Paper Statistics:

Total View : 662 | Downloads : 653 | Page No: 122-124 |

Cite this Article:
Click here to get all Styles of Citation using DOI of the article.