Click Here for
Track Your Paper
ISSN:2454-4116

International Journal of New Technology and Research

Impact Factor 3.953

(An ISO 9001:2008 Certified Online Journal)
India | Germany | France | Japan

Improvement of The ADC Resolution Based on FPGA Implementation of Interpolating Algorithm

( Volume 2 Issue 1,January 2016 ) OPEN ACCESS
Author(s):

Y. Kebbati, A. Ndaw

Abstract:

This paper exposes a method that gives us the possibility to use a low accuracy Analog-to-Digital Converter (ADC) in high-resolution measurements. We increase the resolution of a 12-bits ADC to 16-bits by adding samples which are calculated using Shannon interpolate algorithm. Thus, the digital signal has high resolution compared to measurements. Specific hardware architecture was developed to implement the algorithm in FPGA. The great advantages of the proposed design are an enhancement of ADC resolution and the continuous time is modeled as a white noise which is generated by the FPGA itself, obviating the need of an external noise source. Results were presented in order to confirm the method

Paper Statistics:

Total View : 666 | Downloads : 657 | Page No: 100-103 |

Cite this Article:
Click here to get all Styles of Citation using DOI of the article.